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[pbsd-mg2] Re: cache problem again

I believe that some caching problem still remains.  I'm getting
illegal instructions in kernel mode sometimes for instructions like
	lw	s1, (48)s0
which isn't an illegal instruction.  However, the virtual address
printed out matches the address stored in (48)s0.

I've been running tonight w/o any of the HPCMIPS_* options enabled and
have been seeing this in different places, typically in interrupt
handlers.  When I examine the address, the debugger prints a value.

My sources are from before the 1.4 merge began (Monday or Tuesday),
since I wanted to wait for things to settle down before moving to

Just wanted to let people know this is still going on for me :-(.  I'm 
still trying to track it down completely.