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[pbsd-mg2] Re: Commit NetBSD/hpcmips codes
UCHIYAMA Yasushi <uch@nop.or.jp> writes:
> Jonathan Stone:
> | >I'd like to commit these changes once as they are and change
> | >#ifdef __hpcmips__ appropriately later because change logs will be
> | >recorded in cvs.netbsd.org. As soda-san says, it is more efficient.
> |
> | I understand that goal, but I'd rather the #ifef __hpcmips__ defines
> | in platform-independent, mips-specific (sys/arch/mips) get cleaned up
> | before the commit. Because that's the right thing to do.
>
> mips/以下のパッチはJonathan Stoneに変更してもらって、その後それにあわせて
> hpcmips/以下を変更するばいいんじゃないでしょうか?
> この部分は、とりあえず変更点のマーカーとしての#ifdef __hpcmips__なので
> ここまでくれば早くなくなるに越したことはないと思ってます。
この件ですが、どなたか作業していますか？
Jonathan Stoneの提案と曽田さんの提案の折衷案で、以下のoptionsを使うよう
にしたパッチを作ってみました。進捗がないようでしたら、このパッチを
port-mipsに投げて意見を聞いて、反対がなければcommitしてしまいたいのです
が。
篠原
options MIPS3_4100 /* VR4100 core */
options MIPS_16K_PAGE /* enable kernel support for 16k pages */
options SOFTFLOAT /* No FPU; avoid touching FPU registers */
Index: include/cpuregs.h
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/include/cpuregs.h,v
retrieving revision 1.22
diff -u -r1.22 cpuregs.h
--- cpuregs.h 1999/05/21 06:37:39 1.22
+++ cpuregs.h 1999/09/19 03:56:38
@@ -285,8 +285,14 @@
#define MIPS3_CONFIG_DC_SHIFT 6
#define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
#define MIPS3_CONFIG_IC_SHIFT 9
+#ifdef MIPS3_4100 /* VR4100 core */
+#define MIPS3_CONFIG_CS 0x00001000 /* cache size mode indication*/
#define MIPS3_CONFIG_CACHE_SIZE(config, mask, shift) \
+ ((((config)&MIPS3_CONFIG_CS)?0x400:0x1000) << (((config) & (mask)) >> (shift)))
+#else
+#define MIPS3_CONFIG_CACHE_SIZE(config, mask, shift) \
(0x1000 << (((config) & (mask)) >> (shift)))
+#endif
/* Block ordering: 0: sequential, 1: sub-block */
#define MIPS3_CONFIG_EB 0x00002000
Index: include/locore.h
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/include/locore.h,v
retrieving revision 1.20
diff -u -r1.20 locore.h
--- locore.h 1999/04/24 08:10:35 1.20
+++ locore.h 1999/09/19 03:56:38
@@ -138,8 +138,10 @@
#if defined(MIPS3) && !defined (MIPS1)
#define MachFlushCache mips3_FlushCache
-#if defined(MIPS3_L2CACHE_ABSENT) && !defined(MIPS3_L2CACHE_PRESENT)
-#define MachFlushDCache mips52xx_FlushDCache
+#if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_4100)
+#define MachFlushDCache mips3_FlushDCache /* VR4100 */
+#elif defined(MIPS3_L2CACHE_ABSENT) && !defined(MIPS3_L2CACHE_PRESENT)
+#define MachFlushDCache mips52xx_FlushDCache /* RM5200 */
#elif !defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT)
#define MachFlushDCache mips3_FlushDCache
#else
Index: include/mips3_pte.h
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/include/mips3_pte.h,v
retrieving revision 1.9
diff -u -r1.9 mips3_pte.h
--- mips3_pte.h 1999/05/27 01:56:33 1.9
+++ mips3_pte.h 1999/09/19 03:56:40
@@ -81,9 +81,15 @@
#define MIPS3_PG_WIRED 0x80000000 /* SW */
#define MIPS3_PG_RO 0x40000000 /* SW */
+#ifdef MIPS_16K_PAGE /* enable kernel support for 16k pages */
+#define MIPS3_PG_SVPN 0xffffc000 /* Software page no mask */
+#define MIPS3_PG_HVPN 0xffff8000 /* Hardware page no mask */
+#define MIPS3_PG_ODDPG 0x00004000 /* Odd even pte entry */
+#else
#define MIPS3_PG_SVPN 0xfffff000 /* Software page no mask */
#define MIPS3_PG_HVPN 0xffffe000 /* Hardware page no mask */
#define MIPS3_PG_ODDPG 0x00001000 /* Odd even pte entry */
+#endif
#define MIPS3_PG_ASID 0x000000ff /* Address space ID */
#define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
#define MIPS3_PG_V 0x00000002 /* Valid */
@@ -91,7 +97,11 @@
#define MIPS3_PG_D 0x00000004 /* Dirty */
#define MIPS3_PG_ATTR 0x0000003f
#define MIPS3_PG_UNCACHED 0x00000010
-#define MIPS3_PG_CACHED 0x00000018 /* Cacheable noncoherent */
+#ifdef HPCMIPS_L1CACHE_DISABLE /* MIPS3_L1CACHE_DISABLE */
+#define MIPS3_PG_CACHED MIPS3_PG_UNCACHED /* XXX: brain damaged!!! */
+#else /* HPCMIPS_L1CACHE_DISABLE */
+#define MIPS3_PG_CACHED 0x00000018 /* Cacheable noncoherent */
+#endif /* ! HPCMIPS_L1CACHE_DISABLE */
#define MIPS3_PG_CACHEMODE 0x00000038
/* Write protected */
#define MIPS3_PG_ROPAGE (MIPS3_PG_V | MIPS3_PG_RO | MIPS3_PG_CACHED)
@@ -104,7 +114,11 @@
#define MIPS3_PG_IOPAGE \
(MIPS3_PG_G | MIPS3_PG_V | MIPS3_PG_D | MIPS3_PG_UNCACHED)
#define MIPS3_PG_FRAME 0x3fffffc0
+#ifdef MIPS3_4100 /* VR4100 core */
+#define MIPS3_PG_SHIFT 4
+#else
#define MIPS3_PG_SHIFT 6
+#endif
/* pte accessor macros */
Index: include/mips_param.h
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/include/mips_param.h,v
retrieving revision 1.13
diff -u -r1.13 mips_param.h
--- mips_param.h 1999/04/24 08:10:36 1.13
+++ mips_param.h 1999/09/19 03:56:40
@@ -31,9 +31,15 @@
#define ALIGN(p) (((u_int)(p) + ALIGNBYTES) & ~ALIGNBYTES)
#define ALIGNED_POINTER(p,t) ((((u_long)(p)) & (sizeof(t)-1)) == 0)
+#ifdef MIPS_16K_PAGE /* enable kernel support for 16k pages */
+#define NBPG (1024*16) /* bytes/page */
+#define PGOFSET (NBPG-1) /* byte offset into page */
+#define PGSHIFT 14 /* LOG2(NBPG) */
+#else
#define NBPG 4096 /* bytes/page */
#define PGOFSET (NBPG-1) /* byte offset into page */
#define PGSHIFT 12 /* LOG2(NBPG) */
+#endif
#define NPTEPG (NBPG/4)
#define NBSEG 0x400000 /* bytes/segment */
Index: mips/db_interface.c
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/mips/db_interface.c,v
retrieving revision 1.17
diff -u -r1.17 db_interface.c
--- db_interface.c 1999/05/27 01:56:34 1.17
+++ db_interface.c 1999/09/19 03:56:43
@@ -302,7 +302,7 @@
struct tlb tlb;
int i;
- for (i = 0; i < MIPS3_TLB_NUM_TLB_ENTRIES; i++) {
+ for (i = 0; i < mips_num_tlb_entries; i++) {
mips3_TLBRead(i, &tlb);
db_printf("TLB%c%2d Hi 0%x08x ",
(tlb.tlb_lo0 | tlb.tlb_lo1) & MIPS3_PG_V ? ' ' : '*',
Index: mips/locore.S
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/mips/locore.S,v
retrieving revision 1.76
diff -u -r1.76 locore.S
--- locore.S 1999/08/16 07:53:18 1.76
+++ locore.S 1999/09/19 03:56:47
@@ -99,8 +99,17 @@
#ifdef __GP_SUPPORT__
la gp, _C_LABEL(_gp)
#endif
+#ifdef SOFTFLOAT /* No FPU; avoid touching FPU registers */
+ li t0, 0 # Disable interrupts and
+ mtc0 t0, MIPS_COP_0_STATUS # the fp coprocessor
+#ifdef HPCMIPS_L1CACHE_DISABLE
+ li t0, 0x00018c2 # XXX, KSEG0 is uncached
+ mtc0 t0, MIPS_COP_0_CONFIG
+#endif /* HPCMIPS_L1CACHE_DISABLE */
+#else
li t0, MIPS_SR_COP_1_BIT # Disable interrupts, and
mtc0 t0, MIPS_COP_0_STATUS # enable the fp coprocessor
+#endif
nop
nop
mfc0 t0, MIPS_COP_0_PRID # read product revision ID
@@ -108,7 +117,11 @@
nop # wait for new SR
nop # to be effective
nop
+#ifdef SOFTFLOAT /* No FPU; avoid touching FPU registers */
+ add t1, zero, zero
+#else
cfc1 t1, MIPS_FPU_ID # read FPU ID register
+#endif
sw t0, _C_LABEL(cpu_id) # save PRID register
sw t1, _C_LABEL(fpu_id) # save FPU ID register
jal _C_LABEL(mach_init) # mach_init(a0, a1, a2, a3)
@@ -243,8 +256,21 @@
1:
lw t0, _C_LABEL(whichqs) # look for non-empty queue
nop
+#if defined(MIPS3_4100) && defined(VR41_STANDBY_IDLE)
+ bne t0, zero, 1f
+ nop
+ .word 0x42000021 # standby
+ nop
+ nop
+ nop
+ nop
+ beq t0, zero, 1b
+ nop
+1:
+#else /* MIPS3_4100 && defined(VR41_STANDBY_IDLE) */
beq t0, zero, 1b
nop
+#endif /* MIPS3_4100 && defined(VR41_STANDBY_IDLE) */
la ra, sw1
j ra
mtc0 zero, MIPS_COP_0_STATUS # disable all interrupts
Index: mips/locore_mips3.S
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/mips/locore_mips3.S,v
retrieving revision 1.9
diff -u -r1.9 locore_mips3.S
--- locore_mips3.S 1999/04/24 08:10:40 1.9
+++ locore_mips3.S 1999/09/19 03:56:54
@@ -1267,7 +1267,12 @@
dmtc0 v0, MIPS_COP_0_TLB_HI # Mark entry high as invalid
dmtc0 zero, MIPS_COP_0_TLB_LO0 # Zero out low entry0.
dmtc0 zero, MIPS_COP_0_TLB_LO1 # Zero out low entry1.
+#ifdef MIPS3_4100 /* VR4100 core */
+ lw v0, _C_LABEL(default_pg_mask) # default_pg_mask declared
+ mtc0 v0, MIPS_COP_0_TLB_PG_MASK # in mips_machdep.c
+#else
mtc0 zero, MIPS_COP_0_TLB_PG_MASK # Zero out mask entry.
+#endif
/*
* Align the starting value (t1) and the upper bound (a0).
*/
@@ -1364,7 +1369,7 @@
LEAF(mips3_TLBUpdate)
mfc0 v1, MIPS_COP_0_STATUS # Save the status register.
mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts
- and t1, a0, 0x1000 # t1 = Even/Odd flag
+ and t1, a0, MIPS3_PG_ODDPG # t1 = Even/Odd flag
li v0, (MIPS3_PG_HVPN | MIPS3_PG_ASID)
and a0, a0, v0
dmfc0 t0, MIPS_COP_0_TLB_HI # Save current PID
@@ -1396,7 +1401,12 @@
b 4f
nop
1:
+#ifdef MIPS3_4100 /* VR4100 core */
+ lw v0, _C_LABEL(default_pg_mask) # default_pg_mask declared
+ mtc0 v0, MIPS_COP_0_TLB_PG_MASK # in mips_machdep.c
+#else
mtc0 zero, MIPS_COP_0_TLB_PG_MASK # init mask.
+#endif
dmtc0 a0, MIPS_COP_0_TLB_HI # init high reg.
dmtc0 a1, MIPS_COP_0_TLB_LO0 # init low reg0.
dmtc0 a2, MIPS_COP_0_TLB_LO1 # init low reg1.
@@ -1427,7 +1437,12 @@
b 4f
nop
3:
+#ifdef MIPS3_4100 /* VR4100 core */
+ lw v0, _C_LABEL(default_pg_mask) # default_pg_mask declared
+ mtc0 v0, MIPS_COP_0_TLB_PG_MASK # in mips_machdep.c
+#else
mtc0 zero, MIPS_COP_0_TLB_PG_MASK # init mask.
+#endif
dmtc0 a0, MIPS_COP_0_TLB_HI # init high reg.
dmtc0 a2, MIPS_COP_0_TLB_LO0 # init low reg0.
dmtc0 a1, MIPS_COP_0_TLB_LO1 # init low reg1.
Index: mips/mips_machdep.c
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/mips/mips_machdep.c,v
retrieving revision 1.54
diff -u -r1.54 mips_machdep.c
--- mips_machdep.c 1999/08/16 02:59:23 1.54
+++ mips_machdep.c 1999/09/19 03:56:56
@@ -122,6 +122,14 @@
caddr_t msgbufaddr;
+#ifdef MIPS3_4100 /* VR4100 core */
+#ifdef MIPS_16K_PAGE /* enable kernel support for 16k pages */
+int default_pg_mask = 0x00007800;
+#else
+int default_pg_mask = 0x00001800;
+#endif
+#endif
+
#ifdef MIPS1
/*
* MIPS-I (r2000 and r3000) locore-function vector.
@@ -233,7 +241,7 @@
mips_L1DCacheLSize = MIPS3_CONFIG_CACHE_L1_LSIZE(config,
MIPS3_CONFIG_DB);
- mips_CacheAliasMask = (mips_L1DCacheLSize - 1) & ~(NBPG - 1);
+ mips_CacheAliasMask = (mips_L1DCacheSize - 1) & ~(NBPG - 1);
/*
* Clear out the I and D caches.
@@ -362,6 +370,12 @@
#if 1 /* XXX FIXME: avoid hangs in mips3_vector_init() */
mips3_cacheflush_bug = 1;
#endif
+ break;
+ case MIPS_R4100:
+ cpu_arch = 3;
+ mips_num_tlb_entries = 32;
+ mips3_L1TwoWayCache = 0;
+ mips3_cacheflush_bug = 0;
break;
case MIPS_R4300:
cpu_arch = 3;
Index: mips/pmap.c
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/mips/pmap.c,v
retrieving revision 1.70
diff -u -r1.70 pmap.c
--- pmap.c 1999/09/12 01:17:12 1.70
+++ pmap.c 1999/09/19 03:57:00
@@ -1197,13 +1197,8 @@
/* enter entries into kernel pmap */
pte = kvtopte(va);
- /*
- * XXX more thought... what does ROPAGE mean here?
- * is it correc to set all the ROPAGE bits for mips3,
- * but just the valid (and not read-only) bit on mips1?
- */
if (CPUISMIPS3)
- npte |= vad_to_pfn(pa) | MIPS3_PG_ROPAGE | MIPS3_PG_G;
+ npte |= vad_to_pfn(pa) | MIPS3_PG_G;
else
npte |= vad_to_pfn(pa) | MIPS1_PG_V | MIPS1_PG_G;
Index: mips/trap.c
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/mips/trap.c,v
retrieving revision 1.112
diff -u -r1.112 trap.c
--- trap.c 1999/08/18 04:43:31 1.112
+++ trap.c 1999/09/19 03:57:03
@@ -551,7 +551,17 @@
"uvm_fault(%p (pmap %p), %lx (0x%x), 0, ftype) -> %d at pc %p\n",
map, vm->vm_map.pmap, va, vaddr, ftype, rv, (void*)opc);
#endif
+#ifdef HPCMIPS_FLUSHCACHE_XXX
+#if defined(MIPS3) && defined(MIPS3_L2CACHE_ABSENT)
/*
+ * This code is debug use only.
+ */
+ if (CPUISMIPS3 && !mips_L2CachePresent) {
+ MachFlushCache();
+ }
+#endif
+#endif
+ /*
* If this was a stack access we keep track of the maximum
* accessed stack size. Also, if vm_fault gets a protection
* failure it is due to accessing the stack region outside
@@ -672,6 +682,10 @@
sig = SIGILL;
break; /* SIGNAL */
case T_COP_UNUSABLE+T_USER:
+#ifdef SOFTFLOAT /* No FPU; avoid touching FPU registers */
+ sig = SIGILL;
+ break; /* SIGNAL */
+#endif
if ((cause & MIPS_CR_COP_ERR) != 0x10000000) {
sig = SIGILL; /* only FPU instructions allowed */
break; /* SIGNAL */
@@ -743,8 +757,14 @@
mask = cause & status; /* pending interrupts & enable mask */
#if defined(MIPS3) && defined(MIPS_INT_MASK_CLOCK)
- if ((mask & MIPS_INT_MASK_CLOCK) && CPUISMIPS3)
+ if ((mask & MIPS_INT_MASK_CLOCK) && CPUISMIPS3) {
mips3_intr_cycle_count = mips3_cycle_count();
+ /*
+ * Writing a value to the Compare register,
+ * as a side effect, clears the timer interrupt request.
+ */
+ mips3_write_compare(mips3_intr_cycle_count + mips3_timer_delta);
+ }
#endif
uvmexp.intrs++;